The present invention relates to a process in the formation of a gate-all-around transistor, and more specifically, to protection of a high-K dielectric during reliability anneal on nanosheet structures.
In the evolution of transistor design, the fin field effect transistor (finFET) is a successor of a planar transistor. In finFETs, the transistor channel is formed as a vertical fin with the gate wrapped over the fin between the source and drain regions such that the gate is on three sides of the channel. In comparison with the planar transistor, the finFET provides improved performance for scaled gate lengths. As fin widths decrease and approach 5 nanometers, however, channel width variations may cause variability and mobility loss in finFETs. A gate-all-around FET addresses this variability by placing the gate on all four sides of the channel. A gate-all-around nanowire, for example, is essentially a silicon nanowire with a gate going around the circumference. A gate-all-around nanosheet is a three-dimensional silicon nanosheet with a gate going around all four sides as well as the surface perpendicular to all four sides. The formation of a replacement gate-all-around nanosheet transistor, like the formation of a replacement gate finFET, generally involves the formation of a dummy gate used for source and drain formation followed by removal of the dummy gate and replacement with a metal gate.